That basically says that there is a small chance you will occasionally get either a BSOD or you computer will lock up due to a poor instruction in the L3 chache, specifically the Transition Lookaside Buffer. That's seen mostly when doing virtualizations. The average user will probably never encounter it, but I would want a processor that works without issues like that.Elsie Wahlig said:Erratum 298 will be described as follows: "The processor operation to change the accessed or dirty bits of a page translation table entry in the L2 from 0b to 1b may not be atomic. A small window of time exists where other cached operations may cause the stale page translation table entry to be installed in the L3 before the modified copy is returned to the L2. In addition, if a probe for this cache line occurs during this window of time, the processor may not set the accessed or dirty bit and may corrupt data for an unrelated cached operation. The system may experience a machine check event reporting an L3 protocol error has occurred. In this case, the MC4 status register (MSR 0000_0410) will be equal to B2000000_000B0C0F or BA000000_000B0C0F. The MC4 address register (MSR 0000_0412) will be equal to 26h."
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